1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, in particular, to a method for forming a metal interconnection contact hole in a peripheral circuit region, without damaging the semiconductor substrate.
2. Description of the Background Art
In general, the metal interconnection contacts on a DRAM are formed to at least the substrate in active regions, the gate electrodes, the bit lines and the capacitor plate electrodes. In highly integrated devices, the aspect ratio of a metal interconnection contact hole is typically greater than 10. Therefore, the metal interconnection contact hole is formed when a selection ratio to a deep ultraviolet (DUV) photoresist film used to form the contact pattern is at least 8 in an oxide film etching process. An etching process for forming the contact hole is performed in a reactive ion etch (RIE) system having an intermediate plasma density using a perfluorocarbon containing gas mixture such as C4F8 and Ar, C4F6 and Ar, or C5F8 and Ar.
In a high density plasma system, the selection ratio to the photoresist film is more typically 3 or 4. Accordingly, such systems are not suitable as the etch system for forming the metal interconnection contact holes.
In a conventional method for forming the metal interconnection contact hole, a mask insulating film of the gate electrode or bit line is an oxide film, and thus the etching process can be performed by using gas combinations and parameter that will generate a large amount of polymers, such as C4F8 and Ar.
However, when the mask insulating film of the gate electrode or bit line consists of an SiN or SiON film, a multi-step etching process is required.
A first etching process is performed onto the upper portion of the gate electrode using an etching gas such as a mixture of C4F8 and Ar, in order to obtain a high selection ratio to the photoresist film. A second etching process is then performed on the SiN or SiON film, by employing a mixed gas of CHF3, Ar and O2 or a mixed gas of CF4, Ar and O2, both of which provide better selectivity to the photoresist film.
The semiconductor substrate may be damaged in the two-step etching process. Because the wells of highly integrated devices are shallow, damage to the semiconductor substrate tends to increase contact resistance remarkably. Therefore, the etching process for forming the metal interconnection contact must be generally carried out by using the mixed gas of CHF3, Ar and O2 as the etching gas to obtain the high selection ratio with respect to the semiconductor substrate. In addition, when the mask insulating film is a SiN film, the etching process can be performed by using the mixed gas of CHF3, Ar and O2.
However, when that the mask insulating film is a SiON film, its etching properties vary according to film composition. The general SiON film consists of Si3N4 film and SiO3 film, and thus can be etched by using the mixed gas of CHF3, Ar and O2. However, when the Si-rich SiON (SRON) film is used as an etch barrier film in the etching process according to a self aligned contact (SAC) method for a bit line contact and storage electrode contact, it is very difficult to etch the metal interconnection contact.
The SAC method employing the general SiN film has disadvantages in that transistor properties may be deteriorated due to the high stress within SiN film, tending to lift the gate electrode or bit line, increasing contact junction leakage current. Further, and additional reflection barrier film process is required in the formation of the photoresist film for the gate electrode or bit line.
In order to overcome such disadvantages, the SiN film is typically replaced by the SiO2 film or SiON film. However, when the SiO2 film or SiON film is used, the SAC process for forming the contacts to the bit line and storage electrode cannot be performed with acceptable margins.
Moreover, it is almost impossible to obtain a high selection ratio with respect to both the SiON film and the SiO2 film in the oxide film etching process. Accordingly, because silicon is affected by different etch chemistry than that used to etch the oxide film when Si is added to the SiON to form a Si-rich SiON film, it is possible to obtain an improved etching selection ratio in the oxide etching process.
Thus, the Si-rich SiON film has been utilized as an etch barrier film for the SAC process for forming the bit line contact and storage electrode contact. However, the Si-rich SiON film has the disadvantage when it is used in the metal interconnection contact etching process in that it is generally etched using the mixed gas of CHF3, Ar and O2 or a mixed gas of CF4, Ar and O2. Here, the Si-rich SiON film is etched by using the mixed gas of CHF3, Ar and O2 with a large amount of O2 included to maintain the selection ratio with respect to the photoresist film.
The semiconductor substrate will, however, be damaged by etch chemistry having large amounts of O2. Especially, in the chemical mechanical polishing (CMP) process, the non-uniformity of the insulating films that must be opened to form the metal interconnection contact can be over 2000 xc3x85. As a result, it is difficult to apply a three-step etching process including 1) a high selective etching process for the photoresist film, 2) an etching process for the Si-rich SiON film, and 3) a highly selective etching process for the semiconductor substrate, instead of the two-step etching process.
Accordingly, it is an object of the present invention to provide a method for fabricating a semiconductor device which can form a metal interconnection contact hole by performing a first etching process for removing an interlayer insulating film using a photoresist film pattern as an etch mask, a second etching process for removing an etch barrier film and a mask insulating film, and a third etching process for exposing the semiconductor substrate in the contact areas.
In order to achieve the above-described object of the present invention, in a method for fabricating a semiconductor device for forming a metal interconnection contact hole exposing a gate electrode in a peripheral circuit region of a semiconductor substrate and a presumed portion of a metal interconnection contact on the semiconductor substrate, a method for fabricating a semiconductor device includes the steps of: forming a MOSFET having the gate electrode and source/drain regions on the semiconductor substrate, a mask insulating film pattern being provided at the upper portion of the gate electrode, an insulating film spacer being provided at the side walls of the gate electrode; forming a first interlayer insulating film having a contact plug contacted with a presumed portion of a bit line contact and a storage electrode contact on the semiconductor substrate, and an etch barrier film over the entire structure; forming a bit line and a capacitor contacted with the contact plug, and a second interlayer insulating film; forming a photoresist film pattern exposing a presumed portion of the metal interconnection contact on the second interlayer insulating film over the entire structure; and forming the metal interconnection contact hole by etching the stacked structure of the second interlayer insulating film, the etch barrier film and the mask insulating film pattern, and the stacked structure of the etch barrier film and the first interlayer insulating film according to a three-step etching process, by employing the photoresist film pattern as an etching mask, and removing the photoresist film pattern.